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NXP Semiconductors /LPC43xx /ADC0 /DR[6]

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Interpret as DR[6]

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0V_VREF0RESERVED0 (OVERRUN)OVERRUN 0 (DONE)DONE

Description

A/D Channel Data Register. This register contains the result of the most recent conversion completed on channel n.

Fields

RESERVED

Reserved. Always 0.
V_VREF

When DONE is 1, this field contains a binary fraction representing the voltage on the ADCn input pin selected in Table 727, divided by the voltage on the VDDA pin. Zero in the field indicates that the voltage on the ADCn input pin was less than, equal to, or close to that on VDDA, while 0x3FF indicates that the voltage on ADCn input pin was close to, equal to, or greater than that on VDDA.
RESERVED

Reserved. Always 0.
OVERRUN

This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the V_VREF bits in this register.This bit is cleared by reading this register.
DONE

This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data